Microelectronics, integrated circuits

University of Technology)//Optical Technology. One 2001,27(4). 348-349, 351 error analysis of the mathematical model of the intersection of double CCD coordinates, and proposed the conditions of the optimal structure parameters. Through the method of computer simulation, the structural parameters of the two CCD intersections were optimized, and the optimization results at different target surface sizes were obtained. Theoretically, the conclusion that "optical axis intersects orthogonally" in the coordinate CCD of double CCD is proved. Table 1 Reference 9 (Wood) Low-Voltage C-Type SiGe Microwave Power Heterojunction Bipolar Transistor / Jia Hong-Cai, Chen Pei-Yi, Qian Pei-Xin, Pan Hong-Xi, Huang Jie, Yang Zeng-Min, Li Ming-Yue (Tsinghua University Microelectronics Institute) // Semiconductors The device structure and test results of a low-voltage microwave SiGe power heterojunction bipolar transistor (HBT) are given. The device structure is suitable for applications under low voltage and high current conditions. The comb layout is used for the horizontal layout of the comb emitter strip. The working voltage is 3*4V. In the working state of Class C, the output power can reach 1.65W at the working frequency of 1GHz, and the gain can reach 8dB when the gain is 3V. The collection efficiency is 67.8 %. Shen 5 (wood) 8, microelectronics, integrated circuit nanoelectronics research and prospects / Wen Dianzhong, Li Guodong, Zhao Xiaofeng (Heilongjiang University) Natural Science Journal of Heilongjiang University. One 2001, 18 (3). 59-64, on the basis of expounding the concept, meaning and connotation of nanoscience and technology, focuses on several major areas and development prospects of nanoelectronics research and development in the 21st century. Table 1 Paragraph 44 (Wood) Memory Chip Hierarchical Segmentation P/G Mesh Equivalent Resistance Solution Algorithm/ Yan Hongwei, Yan Xiaolang, Sun Lingling, Ma Qi (Zhejiang University, Department of Electrical and Information Technology) // Circuits and Systems Journal + As the memory chip layout P/ The huge size of the G network is used to calculate the equivalent resistance between nodes in a resistor network. Directly using conventional linear equations to solve the algorithm can not meet the memory space and run-time constraints. Aiming at the characteristics of unbalanced density of layout network network, a hierarchical network segmentation algorithm is proposed in this paper. The global network is hierarchically divided into sub-nets that can be solved, and the equivalent subnet algorithm is used to implement fast calculation of multiple observation points. Table 1 Improved High-Level Power Estimation Method of Reference 6 (Golden) / Yang Jun, Long Xing, Hu Chen, Shi Youhua (Journal of Circuits and Systems, National ASIC System Engineering Research Center, Southeast University). 2001, 6(4). *38- The paper discusses the integrated circuit high-level power estimation method, and proposes a more accurate power estimation method for the linear bit correlation coefficient model, which can be used for power-driven VLSI high-level synthesis. The experimental results show that when the signal is a stationary time series with finite parameters, this estimation method has higher accuracy than the method of replacing the strong correlation correlation coefficient with the correlation coefficient of the original signal, thereby improving the module in VLSI high-level design. Power estimation accuracy. Table 3: Parametric Time-Driven Layout Design for Reference 5 (Gold) Based on 25/xm Process / Han Xiaoxia, Zhang Ming, Wu Wanli, Yao Qingdong (Zhejiang University) Journal of Circuits and Systems. An integrated circuit (1C) developed to the era of system-on-chip (SOC). Ultra deep sub-micron system chips have a large scale. Due to the high complexity and fast system clock frequency, the traditional design flow has been difficult to apply to the design of the system chip because of the limited design scale and the difficulty in timing convergence, and the commonly used flattening scalar quantity. Design of fixed-point RISC core for turbulent flow lines / Wei Jian, Zhang Ming, Zhou Qiongfang, Yu Yan, Yao Qingdong (Zhejiang University) "Journal of Circuits and Systems. 2001, 6(4).

From the perspective of developing instruction-level parallelism ILP, this paper analyzes the architecture characteristics of the super-standard super-pipeline processor, and then gives a fixed-point RISC core design. The design uses a Top-down design method with three pipeline execution units, instruction dynamic scheduling, and a non-blocking-caches mechanism for non-blocking caches. Participation 3 (Gold) SSN Research and Its Application in VLSI Design Flow / Xu Donglin, Guo Xinwei, Xu Zhiwei, Lin Yue, Ren Junyan (Electrical Journal of State Key Laboratory of Applied Integrated Circuits and Systems, Fudan University. 2001, 29(11) 1471-1474 details a key reason why synchronous switching noise (SSN) affects the plausibility of VLSI circuits; the parasitic inductance of the chip-package interface. According to the insertion of the power/ground pins in the chip, reducing the chip- Based on the idea of ​​parasitic inductance of the package interface, a simple and effective method for optimal layout of output driver based on SSN performance was proposed and integrated into the VLSI design flow.The verification was performed using a 0.6 micron CMOS process.The results show that the optimized design can be effective. Reducing the Impact of SSN on VLSI Circuit Reliability Table 2 (G) A Fast Three-Dimensional VLSI Interconnect Capacitor Extraction Method: Virtual Multi-Media Approach Yu Wenjian, Wang Zeyi, Hou Jinsong (Department of Computer Science and Technology, Tsinghua University) Chinese Journal of Electronics.

In this paper, a Quasi-Multiple Medium (QMM) acceleration method based on direct boundary element method is proposed and applied to the calculation of three-dimensional VLSI multi-media interconnect capacitors. The QMM method considers a single-layer medium in a three-dimensional interconnected capacitor to be composed of a plurality of virtual media, thereby greatly reducing the number of non-zero elements in the coefficient matrix, and ultimately reducing computation time and storage space significantly. By comparing the QMM algorithm with non-QMM algorithm and the commercial software Raphael's calculation of the actual three-dimensional interconnection structure, the results show that the QMM calculation can significantly improve the efficiency of capacitance extraction while maintaining the accuracy of calculation. Table 3: Two-dimensional analysis of the surface field distribution of the plate structure of the reference 12 (gold) plane field / He Jin, Zhang Xing, Huang Ru, Wang Yangyuan (Peking University Microelectronics Institute), Chinese Journal of Semiconductors. One 2001, 22(7). 915-918 presents a two-dimensional surface electric field analytical physical model based on a two-dimensional Poisson equation solution for a planar field plate structure. Based on the model, the effect of substrate doping concentration, field plate thickness and length on the distribution of two-dimensional surface field was analyzed. The analytical results of the field distribution and breakdown voltage of the analytical prediction are basically in accordance with the previous numerical analysis. This model provides a theoretical basis for the optimal design of the field plate structure.

Dynamic Characteristics of Micro-Microphones with Reference 11 (Wood) Texture Membrane: Top-down Design Using EDA/GAD Tools/Chen Hao, Liu Litian, Li Zhijian (University of Microelectronics, China General Electric Circuit Simulation Software PSPICE and Finite Element Analysis Software ANSYS A system simulation of a silicon S micro-microphone was performed, the optimum values ​​of various parameters were obtained, and the optimized micro-microphone had a flat response in the audio range.On this basis, a Top-down optimization was proposed. The design method is to accurately predict the behavior of the system and analyze the interaction of various components and their impact on system performance.Table 2 Development and Prospect of (Wood) RF Microelectronic Mechanical System / Yuan Mingwen (Hebei Semiconductor Institute) The latest developments, research contents, and applications of RFMEMS are introduced, including switches, relays, capacitors, inductors, filters, microwaves, and microwave components.2 References 22 (noon) The status and development of SOC / Wu Hongjiang, Zheng Bin (Electronics Department, 13) "Semiconductor information.